Hierarchical identification of untestable faults in sequential circuits

被引:0
|
作者
Raik, Jaan [1 ]
Ubar, Raimund [1 ]
Krivenko, Anna [1 ]
Kruus, Margus [1 ]
机构
[1] Tallinn Univ Technol, Dept Comp Engn, Tallinn, Estonia
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability identification operate at the logic-level and, thus, the methods do not scale. Current paper points out a new class of sequentially untestable faults, called register input logic stuck-on faults. We show that it is possible to identify such faults from the register-transfer level (RTL) description of the circuit. Moreover, we prove by experiments that the considered faults form a large subclass of all the untested faults.
引用
收藏
页码:668 / 671
页数:4
相关论文
共 50 条
  • [1] IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS
    LIANG, HC
    LEE, CL
    CHEN, JE
    IEEE DESIGN & TEST OF COMPUTERS, 1995, 12 (03): : 14 - 23
  • [2] New techniques for untestable fault identification in sequential circuits
    Syal, Marian
    Hsiao, Michael S.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (06) : 1117 - 1131
  • [3] Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
    Taavi Viilukas
    Anton Karputkin
    Jaan Raik
    Maksim Jenihhin
    Raimund Ubar
    Hideo Fujiwara
    Journal of Electronic Testing, 2012, 28 : 511 - 521
  • [4] Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
    Viilukas, Taavi
    Karputkin, Anton
    Raik, Jaan
    Jenihhin, Maksim
    Ubar, Raimund
    Fujiwara, Hideo
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2012, 28 (04): : 511 - 521
  • [5] Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits
    Chen, G
    Reddy, SA
    Pomeranz, I
    21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, : 36 - 41
  • [6] COMBINATIONAL ATPG THEOREMS FOR IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS
    AGRAWAL, VD
    CHAKRADHAR, ST
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (09) : 1155 - 1160
  • [7] Untestable Fault Identification in Sequential Circuits Using Model-Checking
    Raik, Jaan
    Fujiwara, Hideo
    Ubar, Raimund
    Krivenko, Anna
    PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, : 21 - +
  • [8] Testing ''untestable'' faults in three-state circuits
    Wohl, P
    Waicukauski, J
    Graf, M
    14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1996, : 324 - 331
  • [9] Identification of primitive faults in combinational and sequential circuits
    Tekumalla, RC
    Menon, PR
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2001, 20 (12) : 1426 - 1442
  • [10] Identification of robust untestable path delay faults
    Wu, WC
    Lee, CL
    Chen, JE
    JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS, 1997, 20 (05) : 549 - 559