A recursive switched-capacitor decimation filter design for 0.8 MM CMOS technology

被引：0

作者：

Baruqui, FAP ^{[1
]}

Petraglia, A ^{[1
]}

Mitra, SK ^{[1
]}

Franca, JE ^{[1
]}

机构：

[1] UFRJ, EE, COPPE, Programa Engenharia Eletr, BR-21945970 Rio De Janeiro, Brazil

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents the design steps considered in the development of an integrated circuit for a switched-capacitor decimation filter. The design consists of dimensioning the operational amplifiers, capacitances and analog switches, using a supply voltage of 5.5 V for a 0.8 mu m technology. Also shown are electrical simulations using PSPICE 5.0 considering both typical and worst case conditions for practical application in telecommunication systems, for a sampling rate reduction from 48.20 MHz to 16.07 MHz. The filter dissipates approximately 46mW (including the output buffer) at 5.5 V, and presents a flat frequency response within 0.12 dB from de to 3.56 MHz.

引用

页码：468 / 471

页数：4

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