Optimisation of a 4H-SiC enhancement mode power JFET

被引：0
|
作者：
Horsfall, AB [1 ]
Johnson, CM [1 ]
Wright, NG [1 ]
O'Neill, AG [1 ]
机构：
[1] Univ Newcastle, Sch Elect Elect & Comp Engn, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England
来源：
SILICON CARBIDE AND RELATED MATERIALS - 2002 | 2002年 / 433-4卷
关键词：
enhancement mode; junction field effect transistors; optimisation; TCAD simulation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An optimised enhancement mode JFET structure determined by TCAD simulation is presented. The device has been simulated using Medici TCAD software for fabrication in 4H-SiC. Investigations of critical device parameters have been studied allowing for the proposed optimal structure. The forward current and forward blocking voltage are optimised simultaneously by examining the variation of the device switching power, defined in this context as the product of the forward blocking voltage and the forward current density, as a function of the channel width and trench depth. Channel width is shown to have the most dramatic effect on the device performance for this structure. The optimised structure has a blocking voltage of 650V for zero bias gate voltage with a 250 A cm(-2) forward current, at a gate voltage of 2.5V.
引用
收藏
页码：777 / 780
页数：4
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