In-situ shallow trench isolation etch with clean chemistry

被引:0
|
作者
Wang, XK [1 ]
Williams, S [1 ]
Padmapani, N [1 ]
Pan, SH [1 ]
机构
[1] Appl Mat Inc, Silicon Etch Div, Sunnyvale, CA 95054 USA
关键词
D O I
10.1109/IEMT.1998.731070
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
An in-situ hard-mask open and self-clean shallow trench isolation (STI) etch process with a bromine and fluorine based chemistry was developed using an Applied Materials DPS chamber. SEM micrograghs from an etched photoresist-patterned wafer show a desired trench profile with rounded bottom corners and smooth side walls. Quartz crystal micro-balance (QCM) measurements, coupon tests, and a 1000 wafer extended run demonstrate a dean STI process. No dry clean are necessary. The STT step used a chemistry which balanced oxygen passivation with fluorine based etching. More tapered profiles can be achieved by increasing the O2 flow rate. Furthermore, the side wall passivation and oxidation improve the bottom corner rounding, which is desired to minimize stress and current leakage. Fluorine radicals chemically etch the silicon. With increasing fluorine content, the formation of side wall passivation becomes less pronounced, and therefore the trench profile becomes more vertical. This strategy of balancing chemical etchants, passivators, and energetic ions enables tuning of the profile within a wide range. In addition to chemistry, the source power and bias power were all varied. The effect of these parameters on the trench profile angles, corner rounding and microloading are discussed. The simplicity, cleanliness, and excellent profile performance of the process make it a most promising candidate for sub-micron STI manufacturing.
引用
收藏
页码:150 / 154
页数:3
相关论文
共 50 条
  • [1] Sphere defects prevention on Shallow Trench Isolation etch
    Meng, LTD
    Swee, GI
    Bonar, J
    Wei, LY
    Han, H
    Jin, KH
    Wei, PC
    ISSM 2005: IEEE International Symposium on Semiconductor Manufacturing, Conference Proceedings, 2005, : 476 - 478
  • [2] In-situ chamber clean for chromium etch application
    Mao, Zhigang
    Chen, Xiaoyi
    Knick, David
    Grimbergen, Michael
    Chandrahood, Madhavi
    Ibrahim, Ibrahim
    Kumar, Ajay
    PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XV, PTS 1 AND 2, 2008, 7028
  • [3] An improved process, metrology and methodology for shallow trench isolation etch
    Gaddam, S
    Baum, C
    2004 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: ADVANCING THE SCIENCE AND TECHNOLOGY OF SEMICONDUCTOR MANUFACTURING EXCELLENCE, 2004, : 93 - 97
  • [4] In-situ steam generation for shallow trench isolation in sub-100nm devices
    Forstner, HJL
    Nouri, F
    Olsen, C
    11TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED THERMAL PROCESSING OF SEMICONDUCTORS, 2003, : 163 - 166
  • [5] Process optimization for shallow trench isolation etch using computational models
    Huang, Shuo
    Panneerchelvam, Prem
    Huard, Chad M.
    Sridhar, Shyam
    Ventzek, Peter L. G.
    Smith, Mark D.
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, 2023, 41 (05):
  • [6] Wet Etch step modelling to help Shallow Trench Isolation module control
    Roussy, A.
    Gedion, M.
    Crousier, N.
    Pinaton, J.
    Labory, K.
    2011 22ND ANNUAL IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2011,
  • [7] Improving MTBC for Al Etch Using an In-Situ Chamber Clean
    Chen, F.
    Huang, Y.
    Ge, Q.
    Ng, H.
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2013 (CSTIC 2013), 2013, 52 (01): : 301 - 305
  • [8] In-situ metrology for end point detection during chemical mechanical polishing of shallow trench isolation structure
    Zantye, PB
    Mudhivarthi, S
    Kumar, A
    Evans, D
    CHEMICAL-MECHANICAL PLANARIZATION-INTEGRATION, TECHNOLOGY AND RELIABILITY, 2005, 867 : 75 - 80
  • [9] Etch chamber condition-based process control model for shallow trench isolation trench depth control
    Gaddam, S
    Braun, MW
    2005 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: ADVANCING SEMICONDUCTOR MANUFACTURING EXCELLENCE, 2005, : 17 - 20
  • [10] Misalignment Study by Etch Induced Silicon Damage in Single Crystal Etch process for Shallow Trench Isolation Structure
    Lee, J. C.
    Lee, S. J.
    Kim, M. J.
    Lee, S. H.
    Oh, K.
    Lee, J. H.
    Kang, M. S.
    Nam, S. W.
    Roh, Y.
    SOLID STATE TOPICS (GENERAL) - 218TH ECS MEETING, 2011, 33 (31): : 53 - 58