Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

被引:4
|
作者
Jarvinen, Okko [1 ]
Kempi, Ilia [1 ]
Unnikrishnan, Vishnu [1 ]
Stadius, Kari [1 ]
Kosunen, Marko [1 ]
Ryynanen, Jussi [1 ]
机构
[1] Aalto Univ, Dept Elect & Nanoengn, Espoo 02150, Finland
来源
IEEE SOLID-STATE CIRCUITS LETTERS | 2022年 / 5卷
关键词
Analog-to-digital converter (ADC); cyclic-coupled ring oscillator (CCRO); digital calibration; finite-impulse response (FIR); least mean-square (LMS); mismatch; time based; time interleaving; timing skew;
D O I
10.1109/LSSC.2022.3145918
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below -60 dBc while running fully in the background. The operation is demonstrated with an 8x TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.
引用
收藏
页码:9 / 12
页数:4
相关论文
共 50 条
  • [21] Fast and Accurate Estimation of Gain and Sample-Time Mismatches in Time-Interleaved ADCs using On-chip Oscillators
    Santin, E.
    Oliveira, L. B.
    Goes, J.
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012,
  • [22] All-digital background calibration of gain and timing mismatches in time-interleaved ADCs using adaptive noise canceller
    Duc Han Le
    Thi Kim Phuong Dinh
    Van-Phuc Hoang
    Duc Minh Nguyen
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2020, 114 (114)
  • [23] A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs
    Yin, Yong-Sheng
    Liu, Liu
    Chen, Hong-Mei
    Deng, Hong-Hui
    Meng, Xu
    Wu, Jing-Sheng
    Wang, Zhong-Feng
    IEICE ELECTRONICS EXPRESS, 2019, 16 (19):
  • [24] Blind Calibration Method of Gain and Time-skew Mismatches in Time-interleaved ADCs
    Qiu, Yongtao
    Zhou, Jie
    Liu, Youjiang
    Cao, Tao
    2019 INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY (ICMMT 2019), 2019,
  • [25] A Background Timing Skew Calibration Technique in Time-Interleaved ADCs
    Wu, Zekai
    Li, Fule
    Ni, Meng
    Ding, Yang
    Wang, Zhihua
    2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2019,
  • [26] Spectrum distribution-based blind calibration method of mismatches for time-interleaved ADCs
    Zhi, He
    Wang, Hui
    Jia, Minghao
    Xie, Huanqing
    Wu, Jianhui
    ELECTRONICS LETTERS, 2024, 60 (19)
  • [27] An All-Digital Background Calibration Technique for M-Channel Downsampling Time-Interleaved ADCs Based on Interpolation
    Han, Chenxi
    Liu, Shubin
    Zhang, Yuhao
    Feng, Lichen
    Liang, Hongzhi
    Zhu, Zhangming
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (06) : 1896 - 1900
  • [28] Digital Correction of Mismatches in Time-Interleaved ADCs for Digital-RF Receivers
    Takahashi, Tomoya
    Kihara, Takao
    Yoshimura, Tsutomu
    2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2017, : 9 - 12
  • [29] All-digital background calibration technique for timing mismatch of time-interleaved ADCs
    Chen, Hongmei
    Pan, Yunsheng
    Yin, Yongsheng
    Lin, Fujiang
    INTEGRATION-THE VLSI JOURNAL, 2017, 57 : 45 - 51
  • [30] A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs
    Chen, Hongmei
    Yin, Yongsheng
    Deng, Honghui
    Lin, Fujiang
    VLSI DESIGN, 2016,