Test generation for primitive path delay faults in combinational circuits

被引:0
|
作者
Tekumalla, RC
Menon, PR
机构
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a method of identifying primitive path-delay faults in combinational circuits, and deriving robust tests for all robustly testable primitive faults, It uses the concept of sensitizing cubes Pa reduce the search space. This approach helps identify faults that cannot be part of any primitive fault, and avoids attempting test generation for then. Sensitization conditions determined for primitive fault identification are also used in test generation, reducing rest generation effort. Experimental results an some of the ISCAS'85 and MCNC'91 benchmark circuits indicate that they contain a fair number of primitive multiple path delay faults which must be tested.
引用
收藏
页码:636 / 641
页数:6
相关论文
共 50 条
  • [21] Selection of potentially testable path delay faults for test generation
    Murakami, A
    Kajihara, S
    Sasao, T
    Pomeranz, I
    Reddy, SM
    INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 376 - 384
  • [22] Test pattern generation for combinational circuits
    Jisuanji Xuebao, 10 (788-793):
  • [23] COMPLETE TEST-SET GENERATION FOR BRIDGING FAULTS IN COMBINATIONAL-LOGIC CIRCUITS
    BASU, SK
    PAUL, JC
    BHATTACHARJEE, PR
    INFORMATION SCIENCES, 1986, 38 (03) : 257 - 269
  • [24] AN EFFICIENT DELAY TEST-GENERATION SYSTEM FOR COMBINATIONAL LOGIC-CIRCUITS
    PARK, ES
    MERCER, MR
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1992, 11 (07) : 926 - 938
  • [25] Test for detection & location of intermittent faults in combinational circuits
    Ismaeel, AA
    Bhatnagar, R
    IEEE TRANSACTIONS ON RELIABILITY, 1997, 46 (02) : 269 - 274
  • [26] Identification and test generation for primitive faults
    Krstic, A
    Cheng, KT
    Chakradhar, ST
    INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 423 - 432
  • [27] Selecting Close-to-Functional Path Delay Faults for Test Generation
    Pomeranz, Irith
    2020 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2020,
  • [28] Test Generation of Path Delay Faults Induced by Defects in Power TSV
    Shih, Chi-Jih
    Hsieh, Shih-An
    Lu, Yi-Chang
    Li, James Chien-Mo
    Wu, Tzong-Lin
    Chakrabarty, Krishnendu
    2013 22ND ASIAN TEST SYMPOSIUM (ATS), 2013, : 43 - 48
  • [29] Test input generation for supply current testing of bridging faults in bipolar combinational logic circuits
    Kuchii, T
    Hashizume, M
    Tamesada, T
    1998 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, PROCEEDINGS, 1998, : 14 - 18
  • [30] COMPLETE TEST-GENERATION METHOD FOR ALL STUCK-AT FAULTS IN COMBINATIONAL-CIRCUITS
    GURAN, H
    HALICI, U
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1990, 68 (05) : 657 - 666