Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

被引:10
|
作者
Lee, Tsung-Hsueh [1 ]
Abshire, Pamela A. [1 ]
机构
[1] Univ Maryland, Dept Elect & Comp Engn, Syst Res Inst, College Pk, MD 20742 USA
基金
美国国家科学基金会;
关键词
1/f noise; clock generation; frequency divider (FD); jitter model; jitter reduction; ring oscillators (ROs); thermal noise; timing jitter; voltage-controlled oscillators (VCOs); LOW-PHASE-NOISE; LOCKED LOOP; CMOS; PERFORMANCE; DESIGN; VCO; LC;
D O I
10.1109/TVLSI.2016.2541718
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Ring oscillators (ROs) are popular due to their small area, modest power, wide tuning range, and ease of scaling with process technology. However, their use in many applications is limited due to poor phase noise and jitter performance. Thermal noise and flicker noise contribute jitter that decreases inversely with oscillation frequency. This paper describes a frequency-boost technique to reduce jitter in ROs. We boost the internal oscillation frequency and introduce a frequency divider following the oscillator to maintain the desired output frequency. This approach offers reduced jitter as well as the opportunity to trade off output jitter with power for dynamic performance management. The oscillator has 32 operating modes, corresponding to different values for the ring size and frequency division. In a 0.5-mu m CMOS process, the highest oscillation frequency achieved is 25 MHz with a root-mean-square period jitter of 54 ps and a power consumption of 817 mu W at 5 V supply. A jitter model for current-starved oscillators was derived and verified by measurement; a direct relationship between oscillation frequency and jitter was derived and measured. Compared with other oscillators, this design achieves the highest performance in terms of jitter per unit interval and figure-of-merit. The performance is expected to improve in more advanced technologies. The results are summarized to offer design guidance based on the frequency-boost technique.
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页码:3156 / 3168
页数:13
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