A domain decomposition method for the finite element simulation of circuit board interconnects

被引：0
|
作者：
Mao, Kaiyu [1 ]
Tan, Jilin [2 ]
Jin, Jian-Ming [1 ]
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, 1406 W Green St, Urbana, IL 61801 USA
[2] Cadence Design Syst Inc, Chelmsford, MA 01824 USA
来源：
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING | 2007年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
A domain decomposition method (DDM) is developed to improve the efficiency of the finite element simulation of interconnects on multilayered printed circuit boards, which helps reduce memory requirements and CPU time without sacrificing the final accuracy. It takes advantage of the multilayered structure and decomposes the board into several single layers separated by power or ground planes. The simulation of each layer can be carried out independently. Connections between neighboring layers are realized by small holes ('' vias ''), whose computation is accomplished in a trivial final combination procedure. The total memory requirement is only related to the largest single layer. The CPU time is also found to be less than that of the full board simulation. This domain decomposition method further permits a convenient and practical way for parallel computation.
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页码：279 / +
页数：2
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