An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing

A study that involved extending and combining existing FPGA tools to create a tool flow that addresses these bottlenecks is presented. The key contributions of the tool flow include formulation techniques for rapid design-space exploration, a coordination framework for communication and synchronization between tasks in different languages and devices, intermediate fabrics for fast placement and routing (PAR), and tools for performance analysis and bottleneck detection. To reduce design iterations, the tool flow enables early design-space exploration, which we refer to as formulation. Comparing RAT performance predictions with actual performance for the TDFIR application when using different signal sizes ranging from 400 Mbytes down to 50 Mbytes shows only 3% predicted errors. Intermediate fabrics (IF) architectures can potentially implement any fabric, but the tools currently support island-style fabrics with application-specialized computational units (CU) spread across reconfigurable interconnects.