A fully integrated 1.7-3.125 gbps clock and data recovery circuit using a gated frequency detector

被引：0
|
作者：
Yang, RJ [1 ]
Liu, SL
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2005年 / E88C卷 / 08期
关键词：
DLL; CDR; dual loop;
D O I：
10.1093/ietele/e88-c.8.1726
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-mu m CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10(-12) with the data rate from 1.7 Gbps to 3.125 Gbps.
引用
收藏
页码：1726 / 1730
页数：5
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