VLSI IMPLEMENTATION OF SMS4 CIPHER FOR OPTIMIZED UTILIZATION OF FPGA

被引：0
|
作者：
Manoj, G. Sai [1 ]
Sravanthi, B. [1 ]
Thirumal, G. [1 ]
Venishetty, Sudheer Raja [1 ]
机构：
[1] Vaagdevi Coll Engn, Dept ECE, Warangal, Andhra Pradesh, India
来源：
PROCEEDINGS OF THE 2018 SECOND INTERNATIONAL CONFERENCE ON INVENTIVE COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICICCT) | 2018年
关键词：
S box; SMS4; Cipher; VLSI design; Target device FPGA; Encryption; VIRTEX;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
SMS4 is a symmetric encryption algorithm, specifically a block cipher, designed for data encryption which is used in WAPI(Wide authentication and privacy infrastructure). In this paper we evaluate SMS4 encryption algorithm based on S box circuit architecture. The SMS4 block cipher has been implemented in Xilinx Vivado on FPGA Virtex-ultra scale Family. Achieved area is compared with other devices in virtex ultra scale family and Xcvu125-flvb2104-1-i is chosen for its best performance. The simulation results revealed optimization in area.
引用
收藏
页码：1225 / 1231
页数：7
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