High Speed Multiply-Accumulator Coprocessor Realized for Digital Filters.

被引：0
|
作者：
RahulNarasimhan, A. [1 ]
Subramanian, R. Siva [2 ]
机构：
[1] VIT Univ, Sch Elect Engn, Chennai Campus, Madras 600048, Tamil Nadu, India
[2] PSNA Coll Engn & Technol, Dept Elect & Commun, Dindugal 624622, Tamil Nadu, India
来源：
2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES | 2015年
关键词：
Multiply-accumulate; coprocessor; digital filters; ARM processor; Vedic multipliers;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In this paper, an optimized co-processor unit, designed specifically for executing the DSP application is proposed. It can be used as a co-processor for the ACORN ARM processor. The co-processor comprises of one MAC unit, control unit, a 32 bit output registers and register files for storing the input values and other co-efficient. The co-processor is designed to execute a FIR filter. Vedic multiplier and booth multiplier has been used in the MAC unit and comparison is done based on the power, speed and area. The MAC unit has two 16 bit input, one 32 bit input and one 32 bit output.
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页数：4
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