Incremental High-Level Synthesis

被引:0
|
作者
Lavagno, Luciano
Kondratyev, Alex
Watanabe, Yosinori
Zhu, Qiang
Fujii, Mototsugu
Tatesawa, Mitsuru
Nakayama, Noriyasu
机构
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The widespread acceptance of High-level synthesis as a mainstream tool mostly depends on its tight integration with the following RTL-to-GDSII design flow. A key aspect is the handling of so-called Engineering Change Orders (ECOs), i.e. minor changes required to fix small functional bugs or meet performance requirements late in the design cycle. Traditional high-level synthesis has attempted to optimize at best the output logic. However, in the ECO scenario the goal is to implement the required change with as few modifications as possible to the RTL, logic netlist, placed netlist and layout. In this paper we show how, by judiciously changing the internal databases used by the tool to match as much as possible the original design, one can achieve minimal impact and implement ECOs in truly incremental mode, while full-blow re-synthesis would lead to massive unnecessary downstream changes. The tool essentially matches source constructs between the original and the ECO design, and copies as many synthesis decisions as possible from the original design to the ECO design.
引用
收藏
页码:693 / 698
页数:6
相关论文
共 50 条
  • [21] IMPROVING THE PERFORMANCE OF HIGH-LEVEL SYNTHESIS
    MARWEDEL, P
    SCHENK, W
    MICROPROCESSING AND MICROPROGRAMMING, 1989, 27 (1-5): : 381 - 387
  • [22] Net scheduling in high-level synthesis
    Prihozhy, A
    IEEE DESIGN & TEST OF COMPUTERS, 1996, 13 (01): : 26 - 35
  • [23] HIGH-LEVEL SYNTHESIS OF DIGITAL CIRCUITS
    DEMICHELI, G
    ADVANCES IN COMPUTERS, VOL 37, 1993, 37 : 207 - 283
  • [24] DIADES - A HIGH-LEVEL SYNTHESIS SYSTEM
    PERKOWSKI, M
    SMITH, D
    DRISCOLL, M
    LIU, J
    BROWN, J
    1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 1895 - 1898
  • [25] AN ASYNCHRONOUS MODEL FOR HIGH-LEVEL SYNTHESIS
    BRAGE, JP
    MICROELECTRONICS JOURNAL, 1994, 25 (03) : 199 - 213
  • [26] HIGH-LEVEL SYNTHESIS OF DIGITAL CIRCUITS
    DEMICHELI, G
    IEEE DESIGN & TEST OF COMPUTERS, 1990, 7 (05): : 6 - 7
  • [27] Dynamically Scheduled High-level Synthesis
    Josipovic, Lana
    Ghosal, Radhika
    Ienne, Paolo
    PROCEEDINGS OF THE 2018 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS (FPGA'18), 2018, : 127 - 136
  • [28] High-level synthesis of recoverable microarchitectures
    Ohm, SY
    Blough, DM
    Kurdahi, FJ
    EUROPEAN DESIGN & TEST CONFERENCE 1996 - ED&TC 96, PROCEEDINGS, 1996, : 55 - 62
  • [29] Verification of scheduling in high-level synthesis
    Karfa, C.
    Mandal, C.
    Sarkar, D.
    Pentakota, S. R.
    Reade, Chris
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, : 141 - +
  • [30] Separation Logic for High-Level Synthesis
    Winterstein, Felix J.
    Bayliss, Samuel R.
    Constantinides, George A.
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2016, 9 (02)