A scalable embedded JPEG2000 architecture

被引：0

作者：

Zhang, CH ^{[1
]}

Long, Y ^{[1
]}

Kurdahi, F ^{[1
]}

机构：

[1] Univ Calif Irvine, Dept EECS, Irvine, CA 92697 USA

来源：

EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION | 2005年 / 3553卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

It takes more than a good tool to shorten the time-to-market window: the scalability of a design also plays an important role in rapid prototyping if it needs to satisfy various demands. The design of JPEG2000 belongs to such cases. As the latest compression standard for still images, JPEG2000 is well tuned for diverse applications, raising different throughput requirements on its composed blocks. In this paper, a scalable embedded JPEG2000 encoder architecture is presented and prototyped onto Xilinx FPGA. The system level design presents dynamic profiling outcomes, proving the necessity of the design for scalability.

引用

页码：334 / 343

页数：10

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