New stress voiding observations in Cu interconnects

被引：4

作者：

Gregoire, M ^{[1
]}

Kordic, S ^{[1
]}

Ignat, M ^{[1
]}

Federspiel, X ^{[1
]}

Vannier, P ^{[1
]}

Courtas, S ^{[1
]}

机构：

[1] Crolles2 Alliance, F-38926 Crolles, France

来源：

PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2005年

关键词：

D O I：

10.1109/IITC.2005.1499915

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Stress voiding (SV) in Cu vias and lines is investigated on 300mm wafers after storage at temperatures ranging from 175 degrees C to 400 degrees C. Sensitivity to SV in lines decreases with metal pattern density. Microstructural analysis of Cu lines shows that voids are not only found at grain boundaries, but also within the grains, indicating bulk and/or surface diffusion of vacancies. Via resistance increase well above 10% is observed. Both via and line SV is observed below and above zero-stress temperature indicating two mechanisms: vacancy diffusion in combination with tensile stress, and Cu densification under compressive stress. SEM and pattern recognition observations on Cu lines are presented. Line void volume distribution is lognormal, while the distribution of the increase in via resistances is bimodal.

引用

页码：36 / 38

页数：3

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