Output impedance design of parallel-connected UPS inverters

This paper deals with the design of the output impedance of UPS inverters with parallel-connection capability. The inner Control loops are considered in the design of the Controllers that makes possible the power sharing among the UPS modules. In these paralleled units, the power-sharing. outer control loops are based on the P/Q droop method in order to avoid any communication among the modules. The power sharing accuracy is highly sensitive to the output impedance of the inverters, making necessary the tight adjustment of this impedance. Novel control loops are proposed to achieve stable output impedance value, and, therefore, proper power balance is guarantee when sharing both linear and nonlinear loads.