A 3D network of helicates fully assembled by π-stacking interactions

被引：63
|
作者：
Vázquez, M
Taglietti, A
Gatteschi, D [1 ]
Sorace, L
Sangregorio, C
González, AM
Maneiro, M
Pedrido, RM
Bermejo, MR
机构：
[1] Univ Florence, UdR INSTM, I-50019 Sesto Fiorentino, Fi, Italy
[2] Univ Pavia, Dipartimento Chim Gen, Lab Chim Supramol, I-27100 Pavia, Italy
[3] Univ Florence, Dipartimento Chim, I-50019 Sesto Fiorentino, Fi, Italy
[4] Univ Santiago de Compostela, Fac Quim, Dept Quim Inorgan, Santiago De Compostela 15782, Spain
来源：
CHEMICAL COMMUNICATIONS | 2003年 / 15期
关键词：
D O I：
10.1039/b303549b
中图分类号：
O6 [化学];
学科分类号：
0703 ;
摘要：
The neutral dinuclear dihelicate [Cu-2(L)(2)] . 2CH(3)CN (1) forms a unique 3D network in the solid state due to pi-stacking interactions, which are responsible for intermolecular antiferromagnetic coupling between Cu(II) ions.
引用
收藏
页码：1840 / 1841
页数：2
相关论文
共 50 条
  • [41] 3D Stacking Induced Mechanical Stress Effects
    Cherman, V.
    Van der Plas, G.
    De Vos, J.
    Ivankovic, A.
    Lofrano, M.
    Simons, V.
    Gonzalez, M.
    Vanstreels, K.
    Wang, T.
    Daily, R.
    Guo, W.
    Beyer, G.
    La Manna, A.
    De Wolf, I.
    Beyne, E.
    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2014, : 309 - 315
  • [42] Novel Chip Stacking Process for 3D Integration
    Lee, Jaesik
    Fernandez, Daniel M.
    Paing, Myo
    Yeo, Yen Chen
    Gao, Shan
    2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 1939 - 1943
  • [43] Wafer stacking : key technology for 3D integration
    Lagahe-Blanchard, C.
    Aspar, B.
    2009 IEEE INTERNATIONAL SOI CONFERENCE, 2009, : 41 - 44
  • [44] 3D Monolithic Integration: stacking technology and applications
    Radu, Ionut
    Nguyen, Bich-Yen
    Gaudin, Gweltaz
    Mazure, Carlos
    2015 INTERNATIONAL CONFERENCE ON IC DESIGN & TECHNOLOGY (ICICDT), 2015,
  • [45] 3D Stacking Approaches for Mold Embedded Packages
    Braun, T.
    Becker, K. -F.
    Piefke, K.
    Voges, S.
    Thomas, T.
    Toepper, M.
    Fischer, T.
    Kahle, R.
    Bader, V.
    Bauer, J.
    Aschenbrenner, R.
    Lang, K. -D.
    EMPC-2011: 18TH EUROPEAN MICROELECTRONICS & PACKAGING CONFERENCE, 2011,
  • [46] Package stacking in SMT for 3D PCB assembly
    Geiger, D
    Shangguan, D
    Tam, S
    Rooney, D
    IEEE/CPMT/SEMI(R) 28TH INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, 2003, : 261 - 264
  • [47] 3D Stacking of High-Performance Processors
    Emma, Philip
    Buyuktosunoglu, Alper
    Healy, Michael
    Kailas, Krishnan
    Puente, Valentin
    Yu, Roy
    Hartstein, Allan
    Bose, Pradip
    Moreno, Jaime
    2014 20TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA-20), 2014, : 500 - 511
  • [48] Heterogeneous 3D Stacking Technology Developments in ASET
    Ikeda, Hiroaki
    2012 2ND IEEE CPMT SYMPOSIUM JAPAN, 2012,
  • [49] Metrology and Inspection Rquirements for 3D Stacking of ICs
    Halder, Sandip
    Miller, Andy
    Maenhoudt, Mireille
    Beyer, Gerald
    Swinnen, Bart
    Beyne, Eric
    Grant, David
    Marx, David
    Dudley, Russ
    Ford, Maurice
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 615 - 618
  • [50] Thermal Management of Packages with 3D Die Stacking
    Chiu, Chia-Pin
    Chang, Je-Young
    Saha, Sanjoy
    2012 7TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2012,
12345