Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp

被引：4
|
作者：
Karalkar, Sagar P. [1 ]
Ganesan, Vishal [2 ]
Paul, Milova [1 ]
Hwang, KyongJin [1 ]
Gauthier, Robert [3 ]
机构：
[1] GLOBALFOUNDRIES, 60 Woodlands Ind Pk D, Singapore 738406, Singapore
[2] GLOBALFOUNDRIES, Wilschdorfer Landstr 101, D-01109 Dresden, Germany
[3] GLOBALFOUNDRIES, 1000 River Rd, Essex Jct, VT 05452 USA
来源：
2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2021年
关键词：
ESD power clamp; ESD nMOS; Latch up; Holding voltage; TLP; vfTLP; HBM;
D O I：
10.1109/IRPS46558.2021.9405206
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
An effective design for medium voltage ESD nMOS power clamp with layout modification of the source junction in 28nm high voltage CMOS technology is presented. Modification of N+/P+ source segmented design of ESD nMOS shows the most efficient ESD power clamp performance in terms of It2/area and holding voltage among other design structure experiments. With having similar It2 performance and area, the segmented GGNMOS has holding voltage of 1V higher than that of the base line GGNMOS for power pad protection. TLP, vf-TLP, HBM and DC-IV characterization techniques were used to characterize the structure.
引用
收藏
页数：5
相关论文
共 50 条
  • [11] Area-Efficient Power-Rail ESD Clamp Circuit With False-Trigger Immunity in 28nm CMOS Process
    Shen, Zilong
    Wang, Yize
    Zhang, Xing
    Wang, Yuan
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2022, 10 : 876 - 884
  • [12] A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS
    Wang, Chenkun
    Zhang, Feilong
    Lu, Fei
    Chen, Qi
    Li, Cheng
    Wang, Albert
    IEEE ACCESS, 2020, 8 : 87164 - 87172
  • [13] A Novel DTSCR Structure with High Holding Voltage and Enhanced Current Discharge Capability for 28 nm CMOS Technology ESD Protection
    Han, Zeen
    Chen, Shupeng
    Liu, Hongxia
    Wang, Shulong
    Ma, Boyang
    Chen, Ruibo
    Fu, Xiaojun
    MICROMACHINES, 2024, 15 (01)
  • [14] Chip-Level CDM Circuit Modeling and Simulation for ESD Protection Design in 28nm CMOS
    Wang, Han
    Zhang, Feilong
    Li, Cheng
    Di, Mengfu
    Wang, Albert
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 746 - 748
  • [15] Power Optimization Approach of ORCA Processor for 32/28nm Technology Node
    Babayan, Davit
    TENTH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION TECHNOLOGIES REVISED SELECTED PAPERS CSIT-2015, 2015, : 11 - 14
  • [16] Low-power, Wide Supply Voltage Bandgap Reference Circuit in 28nm CMOS
    Neri, Filippo
    Brauner, Thomas
    De Mey, Eric
    Schippel, Christian
    2015 IEEE JORDAN CONFERENCE ON APPLIED ELECTRICAL ENGINEERING AND COMPUTING TECHNOLOGIES (AEECT), 2015,
  • [17] GDNMOS: A new high voltage device for ESD protection in 28nm UTBB FD-SOI technology
    Athanasiou, S.
    Legrand, Charles-Alexandre
    Cristoloveanu, S.
    Galy, Ph
    2016 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2016), 2016, : 151 - 154
  • [18] A Low-Leakage, Hybrid ESD Power Supply Clamp in 65nm CMOS Technology
    Elghazali, Mahdi
    Sachdev, Manoj
    Opal, Ajoy
    2014 IEEE PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2014,
  • [19] New modular bi-directional power-switch and self ESD protected in 28nm UTBB FDSOI advanced CMOS technology
    Galy, Ph.
    Bourgeat, J.
    Marin-Cudraz, D.
    2014 IEEE INTERNATIONAL CONFERENCE ON IC DESIGN & TECHNOLOGY (ICICDT), 2014,
  • [20] The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
    Ker, MD
    Lin, KH
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (08) : 1751 - 1759
12345