Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp

被引：4
|
作者：
Karalkar, Sagar P. [1 ]
Ganesan, Vishal [2 ]
Paul, Milova [1 ]
Hwang, KyongJin [1 ]
Gauthier, Robert [3 ]
机构：
[1] GLOBALFOUNDRIES, 60 Woodlands Ind Pk D, Singapore 738406, Singapore
[2] GLOBALFOUNDRIES, Wilschdorfer Landstr 101, D-01109 Dresden, Germany
[3] GLOBALFOUNDRIES, 1000 River Rd, Essex Jct, VT 05452 USA
来源：
2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2021年
关键词：
ESD power clamp; ESD nMOS; Latch up; Holding voltage; TLP; vfTLP; HBM;
D O I：
10.1109/IRPS46558.2021.9405206
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
An effective design for medium voltage ESD nMOS power clamp with layout modification of the source junction in 28nm high voltage CMOS technology is presented. Modification of N+/P+ source segmented design of ESD nMOS shows the most efficient ESD power clamp performance in terms of It2/area and holding voltage among other design structure experiments. With having similar It2 performance and area, the segmented GGNMOS has holding voltage of 1V higher than that of the base line GGNMOS for power pad protection. TLP, vf-TLP, HBM and DC-IV characterization techniques were used to characterize the structure.
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收藏
页数：5
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