A 65nm CMOS 3.6GHz Fractional-N PLL With 5th-Order ΔΣ Modulation and Weighted FIR Filtering

被引：4
|
作者：
Yu, Xueyi [1 ]
Sun, Yuanfeng [2 ]
Rhee, Woogeun [2 ]
Ko, Sangsoo [3 ]
Choo, Wooseung [3 ]
Park, Byeong-Ha [3 ]
Wang, Zhihua [2 ]
机构：
[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Inst Microelect, Beijing, Peoples R China
[3] Samsung Elect, RF Dev Team, Yongin, Gyeonggi Do, South Korea
来源：
2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2009年
关键词：
PHASE NOISE; SYNTHESIZER;
D O I：
10.1109/ASSCC.2009.5357183
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 3.6GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65nm CMOS. The prototype PLL exhibits nearly -100dBc/Hz in-band noise contribution and -126.8dBc/Hz phase noise at a 3MHz offset from a 1.8GHz carrier. With 5(th)-order single-loop Delta Sigma modulation, the fractional spur levels of -65.6dBc and -58.5dBc are achieved within the bandwidth and near the bandwidth, respectively.
引用
收藏
页码：77 / 80
页数：4
相关论文
共 50 条
  • [1] A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS
    Wu, Wanghua
    Bai, Xuefei
    Staszewski, Robert Bogdan
    Long, John R.
    2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 352 - +
  • [2] Design of a 1-V 3-mW 2.4-GHz Fractional-N PLL Synthesizer in 65nm CMOS
    Lee, Yongho
    Kim, Seungsoo
    Shin, Hyunchol
    PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017), 2017, : 230 - 231
  • [3] A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS
    Huang, Sheng
    Liu, Shubin
    Hu, Jin
    Wang, Riyan
    Zhu, Zhangming
    IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2019, 29 (06) : 397 - 399
  • [4] A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter
    Hussein, Ahmed
    Vasadi, Sriharsha
    Soliman, Mazen
    Paramesh, Jeyanandh
    2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 326 - 326
  • [5] A 3.6GHz 1MHz-bandwidth ΔΣ fractional-N PLL with a quantization-noise shifting architecture in 0.18μm CMOS
    Chiu, Wei-Hao
    Lin, Tsung-Hsien
    IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2011, : 114 - 115
  • [6] A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS
    Grimaldi, Luigi
    Bertulessi, Luca
    Karman, Saleh
    Cherniak, Dmytro
    Garghetti, Alessandro
    Samori, Carlo
    Lacaita, Andrea L.
    Levantino, Salvatore
    2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2019, 62 : 268 - +
  • [7] A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS
    Liu, Hanli
    Siriburanon, Teerachot
    Nakata, Kengo
    Deng, Wei
    Son, Ju Ho
    Lee, Dae Young
    Okada, Kenichi
    Matsuzawa, Akira
    IEICE TRANSACTIONS ON ELECTRONICS, 2018, E101C (04): : 187 - 196
  • [8] A 4.6Tbits/s 3.6GHz Single-cycle NoC Router with a Novel Switch Allocator in 65nm CMOS
    Kumar, Amit
    Kundu, Partha
    Singh, Arvind P.
    Peh, Li-Shiuan
    Jha, Niraj K.
    2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, : 63 - +
  • [9] Low-Noise Fractional-N PLL Design with Mixed-Mode Triple-Input LC VCO in 65nm CMOS
    Sun, Yuanfeng
    Yu, Xueyi
    Rhee, Woogeun
    Ko, Sangsoo
    Choo, Wooseung
    Park, Byeong-Ha
    Wang, Zhihua
    2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM, 2010, : 61 - 64
  • [10] A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS
    Talegaonkar, Mrunmay
    Anand, Tejasvi
    Elkholy, Ahmed
    Elshazly, Amr
    Nandwana, Romesh Kumar
    Saxena, Saurabh
    Young, Brian
    Choi, Woo-Seok
    Hanumolu, Pavan Kumar
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (09) : 2306 - 2320
12345