Low-Noise Fractional-N PLL Design with Mixed-Mode Triple-Input LC VCO in 65nm CMOS

被引：3

作者：

Sun, Yuanfeng ^{[1
]}

Yu, Xueyi ^{[2
,4
]}

Rhee, Woogeun ^{[1
]}

Ko, Sangsoo ^{[3
]}

Choo, Wooseung ^{[3
]}

Park, Byeong-Ha ^{[3
]}

Wang, Zhihua ^{[1
]}

机构：

[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China

[2] Tsinghua Univ, Elect Engn, Beijing 100084, Peoples R China

[3] Samsung Elect, MSC Dev Team, Yongin, Gyeonggi, South Korea

[4] Marvell Tech, Shanghai, Peoples R China

来源：

2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM | 2010年

关键词：

CMOS integrated circuits; LC-VCO; phase-locked loops; phase noise; voltage-controlled oscillators; SYNTHESIZER; LOOP;

D O I：

10.1109/RFIC.2010.5477397

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a low-noise Sigma Delta fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the Sigma Delta fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem caused by the high gain coarse-tuning path. A 3.6GHz Sigma Delta fractional-N PLL implemented in 65nm CMOS exhibits nearly -100dBc/Hz in-band noise contribution and -53dBc in-band fractional spur performances from a 1.8GHz carrier.

引用

页码：61 / 64

页数：4

共 17 条

[1] A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS
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Liu, Shubin
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Zhu, Zhangming
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[2] Design of a 1-V 3-mW 2.4-GHz Fractional-N PLL Synthesizer in 65nm CMOS
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[3] A K-Band Fractional-N Frequency Synthesizer With a Low Phase Noise LC VCO in 90nm CMOS
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[4] A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS
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2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 352 - +
[5] A 65nm CMOS 3.6GHz Fractional-N PLL With 5th-Order ΔΣ Modulation and Weighted FIR Filtering
Yu, Xueyi
Sun, Yuanfeng
Rhee, Woogeun
Ko, Sangsoo
Choo, Wooseung
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Wang, Zhihua
2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2009, : 77 - 80
[6] A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter
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2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 326 - 326
[7] Programmable low-noise fast-settling fractional-N CMOS PLL with two control words for versatile applications
Rana, RS
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2005, 152 (06): : 654 - 660
[8] A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS
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[9] Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs
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Herzel, F.
ADVANCES IN RADIO SCIENCE, 2015, 13 : 133 - 139
[10] A Fractional-N Digital PLL with Background-Dither-Noise-Cancellation Loop Achieving <-62.5dBc Worst-Case Near-Carrier Fractional Spurs in 65nm CMOS
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Chen, Mike Shuo-Wei
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