Development of a Through-Silicon Via (TSV) Process Module for Multi-Project Wafer SiGe BiCMOS and Silicon Interposer

被引：5

作者：

Wietstruck, M. ^{[1
]}

Marschmeyer, S. ^{[1
]}

Kulse, P. ^{[1
]}

Voss, T. ^{[1
]}

Lisker, M. ^{[1
]}

Krueger, A. ^{[1
]}

Wolansky, D. ^{[1
]}

Fraschke, M. ^{[1
]}

Kaynak, M. ^{[1
,2
]}

机构：

[1] IHP, Technol Pk 25, D-15236 Frankfurt, Oder, Germany

[2] Sabanci Univ, Elect Engn, TR-34956 Tuzla, Turkey

来源：

2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) | 2018年

关键词：

Through-Silicon Via; BiCMOS; Interposer; 3D-Integration; Packaging;

D O I：

10.1109/ECTC.2018.00341

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, the development of a Through-Silicon Via process module for multi-project wafer SiGe BiCMOS and silicon interposer is demonstrated. The TSV technology based on a via-middle approach is optimized to provide TSV process and design flexibility which is required for a multi-project wafer service. Different passive and active TSV-based components like a low-noise amplifier, RF interposer transmission lines and substrate-integrated waveguides are fabricated. The TSV process module enables a wide range of promising new applications by adding additional functionalities to conventional BiCMOS and interposer substrate technologies.

引用

页码：2267 / 2274

页数：8

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