Impact of Lithography-friendly Circuit Layout

Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual wafer feature sizes. However, the circuit layout can be modified in a manner which can make it more lithography-friendly. These modifications are implemented as a series of perturbation iterations on the initial layout generated by the CAD tool. The iterations are performed based on estimates of the highest feature variations which are calculated offline for standard cell pairs and stored in a Look-up table (LUT). The iterations are directed by a Simulated Annealing algorithm. In the process we observe the impact of the iterations performed on the initial solution in terms of wirelength, vias and routing congestion. The procedure is validated on ISCAS85 benchmark circuits and a reduction of greater than 20% in the number of instances with the highest cell boundary feature variations is observed. The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2-7.8% respectively for different circuits.