Diagnostic test generation for sequential circuits

Efficient diagnosis of faults in VLSI circuits requires high quality diagnostic test sets. In this work, novel techniques for diagnostic test generation are proposed that require significantly less time than previous methods. The set of fault pairs left undistinguished by a detection-oriented test set is first filtered to target only testable faults. Then diagnostic test generation is performed using a genetic algorithm (GA) combined with a diagnostic fault simulator. A new fitness metric is proposed for the GA that accurately measures the quality of candidate sequences while requiring a limited amount of CPU time. Experimental results illustrate the effectiveness of the approach for sequential circuits.