共 50 条
- [31] Variability and Power Management in sub-100nm SOI Technology for Reliable High Performance Systems 2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2008, : 1 - 4
- [32] Soft-error charge-sharing mechanisms at sub-100nm technology nodes 2007 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2007, : 213 - +
- [35] Test circuits for extracting sub-100nm MOSFET technology variations with the MOSFET model HiSIM ICMTS 2004: PROCEEDINGS OF THE 2004 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2004, : 267 - 272
- [36] Analysis of noise margins due to device parameter variations in sub-100nm CMOS technology PROCEEDINGS OF THE 2007 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2007, : 81 - +
- [37] Application of Cr-less mask technology for sub-100nm gate with single exposure 22ND ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2002, 4889 : 568 - 578
- [38] Electromigration study of sub-100nm Cu-lines ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004), 2004, : 253 - 257
- [39] Intensity weighed focus drilling exposure for maximizing process window of sub-100nm contact by simulation OPTICAL MICROLITHOGRAPHY XX, PTS 1-3, 2007, 6520
- [40] The improvement of DOF for sub-100nm process by focus scan OPTICAL MICROLITHOGRAPHY XIX, PTS 1-3, 2006, 6154 : U1021 - U1029