Plasma processing of high density vias in compliant wafer level package

The demand for maximum functionality, performance and higher packing efficiency in consumer and portable electronic products require the development of high density and high performance wafer level package technology. A novel high density and high performance wafer level packaging technology called the Compliant Wafer Level Package (CWLP) has been developed as a packaging solution for current and future electronic products. In this paper, the use of plasma processing is investigated as a methodology for creating high density vias in the CWLP. The etch characteristics of thick (> 20 mum) polynorbornene films for high density compliant wafer level packages are studied in O-2/CHF3 based plasmas. Two polynorbornene modifications are investigated in this study: one with an epoxy substitute and the other with a silicon substitute. The effects of processing parameters such as RF power chamber pressure, flow rate, gas composition, and mask material on polymer etch rate and via sidewall angle are investigated A novel technique is developed to accurately control the angle of via sidewalls and the polymer etch rare by varying plasma processing conditions. It is observed that the etch rate increases with RF power and chamber pressure. An increase of CHF3/O-2 ratio gives a maximum etch rate at similar to 10% CHF3 for the epoxy substituted polynorbornene and similar to 20% CHF3 Si-containing polynorbornene. The etch rate decreases with total flow rate in O-2/CHF3 plasmas but does not change substantially with flow rate in O-2 plasmas. The sidewall angle is strongly affected by RF power and chamber pressure.