BDD-based synthesis for mixed CMOS/PTL logic

Power consumption and performance are two important design constraints for logic synthesis in design automation. In this paper, we propose an efficient synthesis algorithm to minimize power dissipation and optimize performance of the given digital circuits by constructing a binary decision diagram (BDD) whose nodes can be implemented by CMOS logics and pass-transistor logics (PTL) in a cell library. For BDD mapped circuits, the conventional synthesis algorithms need three cells: the CMOS cell, PTL cell, and CMOS remapping pattern. In the proposed synthesis algorithm, we first refine the cell library structure to two kinds of cells: PTL and CMOS cells. Next, a new algorithm is presented to select the suitable cells so that the areas and power dissipation can be decreased when the logic functions of the given digital circuits are mapped into BDD. The efficiency of this algorithm has been shown in the experimental results. Copyright (C) 2010 John Wiley & Sons, Ltd.