A Low-Power High-Speed 16T 1-Bit Hybrid Full Adder

被引：0

作者：

Agrawal, Priya ^{[1
]}

Raghuvanshi, D. K. ^{[1
]}

Gupta, M. K. ^{[1
]}

机构：

[1] MANIT, Elect & Comm Engn, Bhopal, India

来源：

2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE) | 2017年

关键词：

full adder; hybrid design; low power; high speed; cadence;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The paper presents a new model of low power 1-bit hybrid adder that uses CMOS and Transmission gate technologies together and produces full swing outputs. This adder is compared with the existing Conventional-CMOS (C-CMOS), CPL, TGA, 14T, 24T hybrid adder and 16T hybrid adder in terms of power, delay and power-delay product in 180-nm and 65-nm technology. The simulations were carried on for different voltages and frequencies on the Cadence Virtuoso using the Spectre simulator. The results conclude that the proposed adder consumes 35-40% low power compared to C-CMOS and is 25-50% faster than C-CMOS.

引用

页码：348 / 352

页数：5

共 50 条

[11] HIGH SPEED AREA EFFICIENT 1-BIT HYBRID FULL ADDER
Kumar, Sachin
Kumar, Aman
Bansal, Puneet
2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 682 - 686
[12] A low-power high-speed hybrid CMOS full adder for embedded system
Tung, Chiou-Kou
Hung, Yu-Cherng
Shieh, Shao-Hui
Huang, Guo-Shing
PROCEEDINGS OF THE 2007 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2007, : 199 - +
[13] Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
Navi, Keivan
Kavehei, Omid
Ruholamini, Mahnoush
Sahafi, Amir
Mehrabi, Shima
Dadkhahi, Nooshin
JOURNAL OF COMPUTERS, 2008, 3 (02) : 48 - 54
[14] Performance analysis of low-power 1-bit CMOS full adder cells
Shams, AM
Darwish, TK
Bayoumi, MA
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (01) : 20 - 29
[15] A Low-Power CLA Adder using a 1-bit Hybrid Full-Adder on the 45nm Technology
Bonam, Raghavaiah
Mareedu, Sai Surya
Kumar, J. Prasanth
2024 2ND WORLD CONFERENCE ON COMMUNICATION & COMPUTING, WCONF 2024, 2024,
[16] Low Power High Speed 1-bit Full Adder Circuit Design in DSM Technology
Yadav, Ashish
Shrivastava, Bhawna P.
Dadoria, Ajay Kumar
2017 IEEE INTERNATIONAL CONFERENCE ON INFORMATION, COMMUNICATION, INSTRUMENTATION AND CONTROL (ICICIC), 2017,
[17] Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications
Parameshwara, M. C.
Srinivasaiah, H. C.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (01)
[18] Low Power Ripple Carry Adder Using Hybrid 1-Bit Full Adder Circuit
Bagwari, Ashish
Katna, Isha
2019 11TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS (CICN 2019), 2019, : 124 - 127
[19] Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder
Upadhyay, Rahul Mani
Chauhan, R. K.
Kumar, Manish
ADCAIJ-ADVANCES IN DISTRIBUTED COMPUTING AND ARTIFICIAL INTELLIGENCE JOURNAL, 2022, 11 (04): : 475 - 488
[20] A Survey on Different Modules of Low-Power High-Speed Hybrid Full Adder Circuits
Saraswat, Vivek
Kumar, Ankur
Pal, Pratosh Kumar
Nagaria, R. K.
2017 4TH IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS (UPCON), 2017, : 323 - 328

← 1 2 3 4 5 →