共 50 条
- [31] Design of Novel Through Silicon via Structures for Reduced Crosstalk Effects in 3D IC Applicationse INTELLIGENT COMMUNICATION, CONTROL AND DEVICES, ICICCD 2017, 2018, 624 : 599 - 605
- [32] Performance Characterization of TSV in 3D IC via Sensitivity Analysis 2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010), 2010, : 389 - 394
- [33] Dielectric Quality of 3D Capacitor Embedded in Through-Silicon Via (TSV) 2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 1158 - 1163
- [34] 3D TCAD Modeling For Stress Management In Through Silicon Via (TSV) Stacks STRESS MANAGEMENT FOR 3D ICS USING THROUGH SILICON VIAS: INTERNATIONAL WORKSHOP ON STRESS MANAGEMENT FOR 3D ICS USING THROUGH SILICON VIAS, 2011, 1378 : 53 - +
- [35] Temperature-Dependent Through-Silicon Via (TSV) Model and Noise Coupling 2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, : 247 - 250
- [36] Analytical Model of the Coupling Capacitance between Cylindrical Through Silicon Via and Horizontal Interconnect in 3D IC 2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
- [37] A Novel Circuit Model for Multiple Through Silicon Vias (TSVs) in 3D IC 2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,