Impedance Adapting Compensation for Low-Power Multistage Amplifiers

被引：97

作者：

Peng, Xiaohong ^{[1
]}

Sansen, Willy ^{[2
]}

Hou, Ligang ^{[1
]}

Wang, Jinhui ^{[1
]}

Wu, Wuchen ^{[1
]}

机构：

[1] Beijing Univ Technol, VLSI & Syst Labs, Dept Elect Engn, Beijing 100124, Peoples R China

[2] Katholieke Univ Leuven, ESAT Lab, B-3001 Leuven, Belgium

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2011年 / 46卷 / 02期

关键词：

Multistage; amplifier; amplifiers; compensation; low power; low voltage; impedance adapting; NESTED MILLER COMPENSATION; OPERATIONAL-AMPLIFIER; TRANSCONDUCTANCE; SCHEME;

D O I：

10.1109/JSSC.2010.2090088

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 mu m CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 mu W power with a 1.5 V supply.

引用

页码：445 / 451

页数：7

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