Minimizing the output voltage ripple of a DC/DC power converter by phase locking

被引：1

作者：

Upadhyaya, Prabal ^{[1
]}

Hess, Herbert L. ^{[1
]}

机构：

[1] Univ Idaho, Dept Elect & Comp Engn, MRCI, Moscow, ID 83844 USA

来源：

2007 IEEE WORKSHOP ON MICROELECTRONICS AND ELECTRON DEVICES | 2007年

关键词：

on-chip DC/DC power Converter; high frequency; phase locking;

D O I：

10.1109/WMED.2007.368052

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Reduced passives size and improved quality factor (Q) for an on-chip inductor can be achieved in a fully integrated DC/DC power converter by high frequency switching. This paper presents a high speed closed-loop buck converter that uses phase locking control system to reduce output voltage ripple. A closed-loop DC/DC power converter has been designed in a TSMC-0.25 mu m technology. The power converter takes a 3.3 V DC input and switches at 1.02 GHz to produce output voltage of 1.5 V and 1.8 V DC and stabilizes in less than 600 ns. Design equations and simulation results are presented.

引用

页码：31 / 34

页数：4

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