Design and performance study of phase-locked loop using fractional-order loop filter

被引：41

作者：

Tripathy, Madhab Chandra ^{[1
]}

Mondal, Debasmita ^{[2
]}

Biswas, Karabi ^{[1
]}

Sen, Siddhartha ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Kharagpur 721302, W Bengal, India

[2] Indian Inst Technol, Dept Biosci & Bioengn, Bombay 400076, Maharashtra, India

来源：

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | 2015年 / 43卷 / 06期

关键词：

fractional-order PLL (FPLL); fractional-order loop filter (FLF); fractional-order voltage controlled oscillator (FVCO); constant phase angle; capture range; lock range; fractional capacitor;

D O I：

10.1002/cta.1972

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The present work reports the realization of an analog fractional-order phase-locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer-order counterpart. Copyright (c) 2014 John Wiley & Sons, Ltd.

引用

页码：776 / 792

页数：17

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