Scheduling and Resource Planner Based on Multicriteria Method for Partially Dynamically Reconfigurable Systems

被引：1
|
作者：
Nunez, A. [1 ]
Dondo, J. [1 ]
Beron, M. [2 ]
Sosa, C. [1 ]
Murdocca, M. [1 ]
机构：
[1] Univ Nacl San Luis, Fac Ciecias Fis Matemat & Nat, Dept Elect, San Luis, Argentina
[2] Univ Nacl San Luis, Fac Ciecias Fis Matemat & Nat, Dept Informat, San Luis, Argentina
来源：
IEEE LATIN AMERICA TRANSACTIONS | 2020年 / 18卷 / 02期
关键词：
Multicriteria Methods; LSP; FPGA; Partial and dynamyc reconfiguration;
D O I：
10.1109/tla.2020.9085298
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Dynamically Reconfigurable FPGAs allow to accelerate the reconfiguration process downloading partial bitstreams to those areas created for that. The partial reconfiguration capability allows to share hardware resources between different tasks during the design lifecycle. In this paper we propose an algorithm based on Logic Score of preference (LSP) multicriteria decision method for floor planning, scheduling and order of deployment of these partial bitstreams during design lifecycle. The proposed method is well suited to be implemented in preemptive systems in which the deadline of a critical task can demand the preemption of a lower priority one.
引用
收藏
页码：414 / 421
页数：8
相关论文
共 50 条
  • [21] PaDReH -: A framework for the design and implementation of dynamically and partially reconfigurable systems
    Carvalho, E
    Calazans, N
    Briäo, E
    Moraes, F
    SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2004, : 10 - 15
  • [22] An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs
    Xu, Xiaodong
    Xu, Qi
    Huang, Jinglei
    Chen, Song
    PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2017 (GLSVLSI' 17), 2017, : 403 - 406
  • [23] Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems
    Huang, Jinglei
    Xu, Xiaodong
    Wang, Nan
    Chen, Song
    INTEGRATION-THE VLSI JOURNAL, 2019, 65 : 331 - 343
  • [24] An architecture and task scheduling algorithm for systems based on dynamically reconfigurable shared memory clusters
    Tudruj, M
    Masko, L
    ADVANCED ENVIRONMENTS, TOOLS, AND APPLICATIONS FOR CLUSTER COMPUTING, 2002, 2326 : 197 - 206
  • [25] 3D scheduling based on code space exploration for dynamically reconfigurable systems
    Kaneko, M
    Yokoyama, J
    Tayu, S
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 465 - 468
  • [26] Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems
    Lee, Trong-Yen
    Hu, Che-Cheng
    Lai, Li-Wen
    Tsai, Chia-Chun
    JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, 2010, 26 (04) : 1289 - 1305
  • [27] Virtualizable Hardware/Software Design Infrastructure for Dynamically Partially Reconfigurable Systems
    Huang, Chun-Hsian
    Hsiung, Pao-Ann
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2013, 6 (02)
  • [28] A multicriteria heuristic method to improve resource allocation in multiproject scheduling
    Lova, A
    Maroto, C
    Tormos, P
    EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, 2000, 127 (02) : 408 - 424
  • [29] Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC
    Chen, YH
    Hsiung, PA
    EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005, 2005, 3824 : 489 - 498
  • [30] Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs
    Alismail, Shaden
    Koch, Dirk
    2023 33RD INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL, 2023, : 123 - 129
12345