In band FEC decoder for SONET/SDH at 2.5 Gbit/s and 10 Gbit/s

被引：0
|
作者：
Quiroga, S [1 ]
Torres, D [1 ]
Veloz, A [1 ]
机构：
[1] IPN, CINVESTAV, Dept Elect Engn, Unidad Guadalajara, Guadalajara, Jalisco, Mexico
来源：
2004 1st International Conference on Electrical and Electronics Engineering (ICEEE) | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a quick overview of the BCH codes, which are used on the FEC process. It also specifies general requirements for the implementation of a "in band" FEC decoder module. The designed architecture of the "In band" FEC decoder module presented in this paper uses a (4359, 4320) BCH code, that has capability to detect and correct up to 3 erroneous bits. This module can process SONET/SDH frames at 2.5 Gbit/s and 10 Gbit/s, improving considerably the bit error rate (BER) of optical links of SONET/SDH networks.
引用
收藏
页码：70 / 73
页数：4
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