Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding

被引：1

作者：

Yuan, Haiying ^{[1
]}

Ju, Zijian ^{[1
]}

Sun, Xun ^{[2
]}

Guo, Kun ^{[1
]}

Wang, Xiuyu ^{[1
]}

机构：

[1] Beijing Univ Technol, Coll Elect Informat & Control Engn, Beijing 100124, Peoples R China

[2] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2016年 / 32卷 / 05期

基金：

中国国家自然科学基金;

关键词：

Pattern run-length coding; System-on-a-chip; Test data compression; Flexible runs-aware; Compatible segment; LENGTH; CODES; POWER;

D O I：

10.1007/s10836-016-5595-z

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a flexible runs-aware PRL coding method whose coding algorithm is simple and easy to implement. The internal 2(-n) -PRL coding iteratively codes 2 (n) runs of compatible or inversely compatible patterns inside a single segment. The external N-PRL coding iteratively codes flexible runs of compatible or inversely compatible segments across multiple segments. The decoder architecture is concise. The benchmark circuits verify the flexible runs-aware PRL coding method, the experimental results show it obtains higher compression ratio and shorter test application time.

引用

页码：639 / 647

页数：9

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