The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines

被引：6
|
作者：
Duncan, AA [1 ]
Hendry, DC [1 ]
Gray, P [1 ]
机构：
[1] Univ Aberdeen, Dept Engn, Kings Coll, Aberdeen AB23 3UE, Scotland
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2001年 / 9卷 / 01期
基金：
加拿大自然科学与工程研究理事会;
关键词：
allocation; compiler; custom computing; DSP synthesis; FCCM; field programmable gate array (FPGA) synthesis; high-level synthesis; partitioning; scheduling; simulated annealing; VLIW;
D O I：
10.1109/92.920837
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the column oriented butted regular architecture-algorithmic behavioral synthesis (COBRA-ABS) high-level synthesis tool which has been designed to synthesize DSP algorithms, specified in C, onto multi-field programmable gate array (FFGA) custom computing machines (FCCMs). COBRA-ABS performs synthesis using a new simulated annealing-based methodology, which maps the specified behavior into a four-dimensional (4-D) space and then optimizes the implied architecture. COBRA-ABS synthesizes custom very long instruction word (VLIW) style architectures partitioned across the FPGAs of the FCCM and has been used to compile C algorithms down to FPGA configuration bit-streams, This paper describes the tool and synthesis concepts and presents simulation results from a number of synthesized fast Fourier transform (FFT) related algorithms.
引用
收藏
页码：218 / 223
页数：6
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