Impact of lead free solder materials on board level reliability for low-K WLCSP

The wafer level chip scale packaging (WLCSP) is a new concept package in which the entire assembly process is completed at the wafer level. The WLCSP fulfills the demand for small, light, and portable handheld electronic devices. The WLCSP is one of the most advanced packaging concepts. The board level reliability is the key issue for the WLCSP, especially for the evaluation of the thermal fatigue life of solder joints. Many papers have discussed the topic for the board level reliability of the WLCSP [1-6]. However, most of these papers focus on evaluating the fatigue life of solder joints for non-low-K WLCSP. This work evaluates the solder ball materials effect on the board level reliability, including the multiple reflow tests, the TCT (-40 inverted perpendicular C similar to 125 degrees C) and the drop test using low-K WLCSP. The structure of the test vehicle is six copper layers with a low-K dielectric constant value of 2.9, produced by the CVD process by using 300mm diameter wafer. The chip size of the test vehicle is 8mm x 8mm x 0.775mm with a 400 mu m solder ball pitch. The evaluated solder ball composition includes SAC205, SAC266, and SAC105. The diameter of the solder ball is 250 mu m. The polyimide with the thickness of 5um was deposited on the low-K wafer prior to the solder balls attachment to enhance the stress buffer capability. This work uses the ball attachment to replace the printing or electroplating process to deposit the solder balls on the wafer. The HTST (150 degrees C) and ten-time multiple reflow tests were used as the low-K wafer level reliability test items. The wafer level test results indicate that all the three solder materials pass both the HTST and the ten-time multiple reflow test. The dimension of the printing circuit board (PCB) is 132.0 mm x 77.0 mm x 1.0 mm. Totally, 18 pcs low-K WLCSP specimens were mounted on the PCB. After the WLCSP specimens were placed on the PCB, the daisy chain will be connected between the WLCSP and PCB test pads and will be used to detect the resistance variance during the board level reliability test. The four-time multiple reflow test, TCT and drop test were implemented to evaluate the board level reliability test. From the board level test results, all the three solder materials pass the four-time multiple reflow tests. Next, the first failure of the drop test time for the SAC105, SAC 205 and SAC 266 is 67, 30 and 28, respectively. Besides, the 63.2% cumulative distribution function (CDF) of TCT of the board level reliability for the SAC105, SAC 205 and SAC 266 is 338 cycles, 307 cycles and 284 cycles, respectively. In the TCT and the drop tests of the board level reliability, the failures occurred within the bumps. The low-K chip and PCB show no delamination or crack failure. This finding indicates the SAC 105 has the preferred resistance to the drop test and the TCT test. Furthermore, the SAC266 has the worst resistance to the drop test and the TCT test Key words: WLCSP, Reliability, Drop test, TCT.