Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache

Einering Nan-Volatile Memories (NVM) such as Spin-Torque Transfer RAM (SIT-RAM) and Resistive RAM (RRAM) have been explored as potential alternatives, for traditional SRAM-based Last-Level-Caches (LLCs) due to the benefits of higher density and lower leakage power: However; NVM technologies have long latency and high energy overhead associated with the write operations. Consequently, a hybrid STT-RAM and SRAM based architecture has been proposed in the hope of exploiting high density and low leakage power of STT-RAM and low write overhead of SRAM. Such a hybrid cache design relies on an intelligent block placement policy that makes good use of the characteristics of both STT-RAM and SRAM technology. In this paper, we propose an adaptive block placement and migration policy (APM) for hybrid caches. LLC write accesses are categorized into three classes: prefetch-write, demand-write, and core-write. Our proposed technique places a block into either SIT-RAM lines or SRAM lines by adapting to the access pattern of each class. An access pattern predictor is proposed to direct block placement and migration, which can benefit from the high density and low leakage power of STT-RAM lines as well as the low write overhead of SRAM lines. Our evaluation shows that the technique can improve performance and reduce PLC power consumption compared to both SRAM-based LLC and STT-RAM-based LLCs he same area footprint. It outperforms the SRAM-based LLC on average by 8.0% for single-thread workloads and 20.5% for multi-core workloads. The technique reduces power consumption in the LLC by 18.9% and 19.3% for single-thread and multi-core workloads, respectively.