UVM-based Functional Coverage Driven AXI4-Stream Verification

With the increasing complexity of modern silicon chips, verification for SoCs is also facing huge challenges. Traditional verification methodologies which cannot meet the time-to-market requirement is being replaced by UVM, a state of art verification methodology. An UVM-based out of box AXI4-Stream verification IP featuring functional coverage model is designed in this paper. With constrained random test, base test and direct test, simulation results show that the function of this verification IP is correct and can be used to verify any IP cores and SoCs featuring AXI4-Stream interface with improved verification efficiency.