共 50 条
- [1] How to Design Hardware Prime Field Multipliers for Bilinear Pairing 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2016, : 203 - 204
- [2] Parallel hardware architectures for the cryptographic Tate pairing THIRD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY: NEW GENERATIONS, PROCEEDINGS, 2006, : 186 - +
- [3] Asynchronous cryptographic hardware design 2006: 40th Annual IEEE International Carnahan Conferences Security Technology, Proceedings, 2006, : 221 - 227
- [4] Hardware Design of Cryptographic Accelerator 2018 IEEE 16TH WORLD SYMPOSIUM ON APPLIED MACHINE INTELLIGENCE AND INFORMATICS (SAMI 2018): DEDICATED TO THE MEMORY OF PIONEER OF ROBOTICS ANTAL (TONY) K. BEJCZY, 2018, : 201 - 206
- [7] Investigation and Design of the Efficient Hardware-based RNG for Cryptographic Applications 2014 2ND INTERNATIONAL CONFERENCE ON ELECTRONIC DESIGN (ICED), 2014, : 255 - 260
- [8] A design of hardware cryptographic co-processor IEEE SYSTEMS, MAN AND CYBERNETICS SOCIETY INFORMATION ASSURANCE WORKSHOP, 2003, : 234 - 236
- [9] Design of cellular automata hardware for cryptographic applications 2004 International Semiconductor Conference, Vols 1and 2, Proceedings, 2004, : 463 - 466
- [10] Design of Cryptographic Hardware Architecture for Mobile Computing JOURNAL OF INFORMATION PROCESSING SYSTEMS, 2009, 5 (04): : 187 - 196