Segmented Successive Cancellation List Polar Decoding with Joint BCH-CRC Codes

Polar codes, which have been adopted as the channel code for 3GPP eMBB control channel, are the first codes achieving the capacity of symmetric binary-input discrete memoryless channels (B-DMCs). For short length polar codes, which are favorable for control channels, CRC-aided segmented successive cancellation list (SCL) decoding can reduce the hardware complexity and memory cost. However, CRC brings no performance gain in segmented decoding. In this paper, an efficient joint decoding scheme called BCH-CRC-aided segmented SCL decoding (BC-SCL) is firstly proposed. Its HARQ refined version is also given. BCH and CRC are employed in different segments to maximize their own correction or check advantages. Numerical results on binary-input additive white Gaussian noise (BI-AWGN) channel have shown the performance gain of the proposed BC-SCL decoder. The corresponding hardware architecture is also proposed. Short-length BC-SCL decoder with (N = 128, K = 64, L = 2) is implemented with Altera Stratix V FPGA. Compared to the CRC-aided decoder, the proposed decoder requires only 76.12% ALMs with slightly increased latency. Therefore, BC-SCL scheme can highly demonstrate advantages of both BCH and CRC in polar segmented decoding.