Reliability engineering enabling continued logic for memory device scaling

被引:3
|
作者
O'Sullivan, B. J. [1 ]
Ritzenthaler, R. [1 ]
Litta, E. Dentoni [1 ]
Simoen, E. [1 ]
Machkaoutsan, V. [2 ]
Fazan, P. [2 ]
Ji, Y-H [3 ]
Kim, C. [3 ]
Spessot, A. [1 ]
Linten, D. [1 ]
Horiguchi, N. [1 ]
机构
[1] imec, Leuven, Belgium
[2] Micron, Boise, ID USA
[3] SK Hynix, Icheon Si, Gyeonggi Do, South Korea
关键词
DRAM periphery; Logic for memory; Reliability; High voltage devices; NBTI; defect band access; AlOx cap; TECHNOLOGY;
D O I
10.1109/iirw47491.2019.8989891
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-kappa metal-gate (HKMG) components into the logic and high-voltage (e.g. I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high-kappa layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high-kappa layers on the Negative Bias Temperature Instability (NBTI) of high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high-kappa processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx, and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-kappa fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.
引用
收藏
页码:1 / 11
页数:11
相关论文
共 50 条
  • [1] Memory Technology: Innovations needed for continued technology scaling and enabling advanced computing systems
    Chandrasekaran, Naga
    Ramaswamy, Nirmal
    Mouli, Chandra
    2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
  • [2] Advances in Logic Device Scaling
    Bansal, Anil Kumar
    Dixit, Abhisek
    IETE TECHNICAL REVIEW, 2015, 32 (04) : 311 - 318
  • [3] Reliability Challenges for the Continued Scaling of IC Technologies
    Oates, Anthony S.
    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
  • [4] Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors
    Nunez-Yanez, Jose
    MICROPROCESSORS AND MICROSYSTEMS, 2017, 51 : 227 - 238
  • [5] Next Generation Gate-all-around Device Design for Continued Scaling Beyond 2 nm Logic
    Vyas, Pratik B.
    Zhao, Charisse
    Dag, Sefa
    Pal, Ashish
    Bazizi, El Mehdi
    Ayyagari-Sangamalli, Buvna
    2023 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, SISPAD, 2023, : 57 - 60
  • [6] Next Generation Gate-all-around Device Design for Continued Scaling Beyond 2 nm Logic
    Vyas, Pratik B.
    Zhao, Charisse
    Dag, Sefa
    Pal, Ashish
    Bazizi, El Mehdi
    Ayyagari-Sangamalli, Buvna
    International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2023, : 57 - 60
  • [7] EFFECT OF DEVICE RELIABILITY ON MEMORY RELIABILITY
    HUMPHRY, JA
    IEEE TRANSACTIONS ON RELIABILITY, 1980, 29 (05) : 416 - 421
  • [8] Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling
    Veloso, A.
    Eneman, G.
    De Keersgieter, A.
    Jang, D.
    Mertens, H.
    Matagne, P.
    Litta, E. Dentoni
    Ryckaert, J.
    Horiguchi, N.
    2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM), 2021,
  • [9] Enabling scaling of advanced CMOS technologies: A reliability perspective
    Nigam, Tanya
    Kerber, Andreas
    2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2015, : 199 - 203
  • [10] Phase Change Memory: Device scaling and challenges for material engineering in the GeSbTe compound system
    Boniardi, Mattia
    Redaelli, Andrea
    MICROELECTRONIC ENGINEERING, 2015, 137 : 1 - 4