Multi-story power delivery for supply noise reduction and low voltage operation

被引:18
|
作者
Gu, J [1 ]
Kim, CH [1 ]
机构
[1] Univ Minnesota, Minneapolis, MN 55455 USA
关键词
multi-story power delivery; supply noise; digital voltage regulator; capacitive coupling;
D O I
10.1109/LPE.2005.195513
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a multi-story power delivery scheme which shows significant reduction of supply noise and power consumption compared to conventional power delivery scheme. To maximize the effectiveness of the proposed scheme, a digital voltage regulator is designed to balance the current dissipation of circuits in different voltage domains. Data transfer circuits based on capacitive coupling are developed for efficient inter-story data communication. Simulation results show 66% and 67% reduction of IR noise and Ldi/dt noise, respectively, while the total power consumption was reduced by 5% compared to a conventional power delivery scheme.
引用
收藏
页码:192 / 197
页数:6
相关论文
共 50 条
  • [21] Low-Power Level Shifter for Multi-Supply Voltage Designs
    Lanuzza, Marco
    Corsonello, Pasquale
    Perri, Stefania
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2012, 59 (12) : 922 - 926
  • [22] Low Noise LDO Architecture with Consideration for Low Voltage Operation
    Mihhailov, Juri
    Strik, Viktor
    Strik, Sergei
    Rang, Toomas
    2014 PROCEEDINGS OF THE 14TH BIENNIAL BALTIC ELECTRONICS CONFERENCE (BEC 2014), 2014, : 41 - 44
  • [23] A Low Supply Voltage Dualband Low Noise Amplifier Design
    Hsiao, Chih-Lung
    Huang, Yi-Lun
    ISCE: 2009 IEEE 13TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2, 2009, : 464 - 466
  • [24] A CAD Approach for On-Chip PDN with Power and Supply Noise reduction for Multi-Voltage SoCs in Pre-Layout Stage
    Chakraborty, Moumita
    Saha, Debasri
    Chakrabarti, Amlan
    2017 7TH INTERNATIONAL SYMPOSIUM ON EMBEDDED COMPUTING AND SYSTEM DESIGN (ISED), 2017,
  • [25] CMOS voltage buffer for extremely low supply operation
    Univ of Technology and Agriculture, Bydgoszcz, Poland
    Electron Technol (Warsaw), 3 (288-292):
  • [26] All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation
    Chae, Kwanyeob
    Mukhopadhyay, Saibal
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2012, 59 (12) : 893 - 897
  • [27] Glitching power reduction through supply voltage adaptation mechanism for low power array structure design
    Hong, SJ
    Chin, SS
    Sadasivam, M
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 733 - 736
  • [28] Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits
    Pant, P
    De, VK
    Chatterjee, A
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1998, 6 (04) : 538 - 545
  • [29] Ultra low voltage operation with bootstrap scheme for single power supply SOI-SRAM
    Iijima, Masaaki
    Kitamura, Masayuki
    Numa, Masahiro
    Tada, Akira
    Ipposhi, Takashi
    20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 609 - +
  • [30] Reduction of Power Supply Voltage for the CMOS Exponentiation Conversion IC Effectively Utilizing Weak Inversion Operation
    Nishiyama, Naoya
    Matsui, Fumiya
    Sano, Yuji
    IEEJ Transactions on Electronics, Information and Systems, 2022, 140 (10) : 1081 - 1090