Hierarchical hard IP reuse in SOC

被引：0
|
作者：
Yun, C [1 ]
Wei, X [1 ]
Ping, L [1 ]
机构：
[1] Univ Elect Sci & Technol China, Inst Microelect, Chengdu 610054, Peoples R China
来源：
2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4 | 2002年
关键词：
SOC; hard IP; reuse; design flow;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A SOC design process with associated hierarchical hard IP reuse is proposed, in which hierarchical module partitioning can cope with the large scale of SOC. This methodology significantly reduces the time-to-market, complexity and potential for errors associated with SOC integration.
引用
收藏
页码：1449 / 1453
页数：5
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