Low-Complexity High-Performance Low-Density Parity-Check Encoder Design for China Digital Radio Standard

This paper proposes a novel encoder architecture of low-density parity-check (LDPC) generator matrix in frequency modulation-China digital radio (CDR), which was promulgated in August 2013. We utilize the specific structure of LDPC parity matrix to parallelize row and column encoding operations. An optimized method is also proposed to control memories, which can be reused for the LDPC code with different code rates to improve the utilization of hardware resources. The proposed LDPC encoder and decoder are implemented on Xilinx FPGA. According to simulation results of ModelSim and MATLAB, we also verify that the proposed method has the advantages of reduced resource consumption, low power, and high accuracy. The proposed encoder can achieve throughput up to 400 Mbps. In particular, with Lena binary image as the test transmission data, we find that the decoded result meets the error requirements of CDR.