Fast power loss calculation for digital static CMOS circuits

被引：3
|
作者：
Gavrilov, S
Glebov, A
Rusakov, S
Blaauw, D
Jones, L
Vijayan, G
机构：
来源：
EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/EDTC.1997.582392
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present a new dynamic power estimation method that produces accurate power measures at considerably faster run rimes. The approach uses an enhanced switch-level simulation algorithm that takes into account both short-circuit power and charge-sharing power effects. In benchmarks against a popular commercial power simulation tool, our approach yields power measurements on average within 3% of the commercial solution, while taking between 15 to 20 times less CPU time.
引用
收藏
页码：411 / 415
页数：5
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