FPGA-based lookup circuit for session-based IP packet classification

被引：0
|
作者：
Abdelghani, Motasern [1 ]
Sezer, Sakir [1 ]
Garcia, Erni [1 ]
Mu, Jun [1 ]
Toal, Ciaran [1 ]
机构：
[1] Queens Univ Belfast, Inst Elect Commun & Informat Technol, Belfast BT12 6BJ, Antrim, North Ireland
来源：
NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS, PROCEEDINGS | 2007年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present the architecture and implementation of an FPGA-based lookup circuit for a session-based IP packet classifier. The concept of session-based packet classification is summarized and the difference between the traditional- and session-based-classification is discussed. A preliminary hardware based architecture customised for FPGA technology is explored and its implementation using Altera Cyclone II technology is outlined A detailed circuit analysis is presented
引用
收藏
页码：619 / +
页数：3
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