DefSim - the educational integrated circuit for defect simulation

被引：4

作者：

Pleskacz, WA ^{[1
]}

Borejko, T ^{[1
]}

Gugala, T ^{[1
]}

Pizon, P ^{[1
]}

Stopjakova, V ^{[1
]}

机构：

[1] Warsaw Univ Technol, Inst Microelect & Optoelect, PL-00661 Warsaw, Poland

来源：

2005 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC SYSTEMS EDUCATION, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/MSE.2005.24

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper the educational integrated circuit DefSim is described This chip is dedicated to development of students' skills in fault simulation and test pattern generation for digital circuits. It allows applying both voltage and current test methods and offers comparing of their efficiencies on basic digital circuit examples. DefSim was manufactured and its operation was verified experimentally.

引用

页码：121 / 122

页数：2

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