A Power-Delay and Area Efficient Voltage Level Shifter Based on a Reflected-Output Wilson Current Mirror Level Shifter

This brief presents an area-efficient and ultra-low power high-speed voltage level shifter (LS) based on a reflected-output Wilson current mirror LS (WCMLS). The proposed technique removes the limitation of conventional WCMLS in using a current mirror with extremely high sizing ratio significantly saving area and power. Compared to the state-of-the-art counterparts, the proposed LS comprises relatively fewer elements all minimum sized further reducing the area. The proposed LS operates well with extremely sub-threshold input voltages while exhibiting considerably lower propagation delay. Implemented in a standard 0.18-mu m CMOS process, post-layout simulations confirm that the proposed subthreshold LS can effectively transform input voltage levels as low as 50 mV to about 1.8 V at output without employing any multi-threshold devices. With an area of 7.5 mu m x 4.7 mu m, the overall delay and power consumption of the proposed LS for a 0.4 V/1 MHz input signal and 1.8 V output level are 6.1 ns and 76.34 nW, respectively.