Electrical Characterization of a High Speed HBM Interface for a Low Cost Interposer

被引:8
|
作者
Dittrich, Michael [1 ]
Heinig, Andy [1 ]
Hopsch, Fabian [1 ]
机构
[1] Fraunhofer IIS EAS, Zeunerstr 38, Dresden, Germany
来源
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) | 2018年
关键词
based integration; heterogeneous integration; copper pillar; C4; bumps; interconnection; electrical simulation;
D O I
10.1109/ECTC.2018.00310
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The demand for higher data rates is still ongoing. But the physical laws are limiting the recent approach of using higher and higher speeds. This leads to a switch from very high-speed on a limited number of ports to reduced speed but with much more ports in parallel. One example for doing this is the High-Bandwidth-Memory (HBM). The paper presents the results of a topology evaluation and the simulations results of the HBM interface to and ASIC across a low cost interposer. Furthermore the design process for a silicon interposer using an Assembly Design Kit is presented. Based on the simulation and the developed design process a system with an ASIC and 8 HBM dies assembled on an interposer was built.
引用
收藏
页码:2068 / 2073
页数:6
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